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1 power mosfet features ? ultra low gate charge ? reduced gate drive requirement ? enhanced 30 v, v gs rating ? reduced c iss , c os s , c rs s ? extremel y high frequency operation ? repetitive avalanche rated ? compliant to rohs directive 2002/95/ec no tes a. repetitive rating; pulse widt h l imited by maximum junction temperature (see fig. 11). b. v dd = 50 v , start ing t j = 25 c, l = 25 mh, r g = 25 ? , i as = 6.2 a (see fig. 12). c. i sd ? 6.2 a , di/dt ? 80 a/s, v dd ? v ds , t j ? 150 c. d. 1.6 mm from case. pr oduc t summary v ds (v) 600 r ds(on ) ( ? )v gs = 10 v 2.2 q g (max.) (nc) 39 q gs (nc) 10 q gd (nc ) 19 configuration single n-channel mosfet g d s av ailable rohs* compliant absolute maxim um ra tings (t c = 25 c, unless otherwise noted) parame te r s ymbol limit unit drain-source voltage v ds 600 v gate-source v oltage v gs 30 continuous drain cu rrent v gs at 10 v t c = 25 c i d 4 a t c = 100 c 2.9 pul sed d rain current a i dm 25 linear derating factor 1.0 w /c sing le pulse avalanche energy b e as 530 mj re petitiv e avalanche current a i ar 6.2 a r epetitive avalanche energy a e ar 13 mj maxi mum po wer dissipation t c = 25 c p d 125 w p ea k diode recovery dv/dt c dv/dt 3.0 v /ns operati n g junction and storage temperature range t j , t stg - 55 to + 150 c soldering recommendations (p eak temperature) for 10 s 300 d mou nting torque 6-32 or m3 screw 10 lbf in 1.1 n m * p b co ntaining terminations are not rohs compliant, exemptions may apply t o-220ab t op v i e w gd s s d g t o-220 fullpak t o-252 s gd top v ie w to-251 s d g top view top v ie w dt p4n60 DTP4N60F dtu4n60 dtl4n60 www.din-tek.jp dt p4n60/DTP4N60F/dtu4n60/dtl4n60
2 not es a. repetitive rating; pulse widt h limited by maximum junction tem perature (see fig. 11). b. pulse width d 300 s; duty cycle d 2 %. t h er mal res i sta nce ratings parameter symb ol typ. max . unit maximum junction-to -ambient r thj a -6 2 c /w cas e-to-sink, flat, greased surface r th cs 0.50 - maxi mum junction-to-case (drain) r th jc -1 . 0 specifi cations (t j = 25 c, unless otherwise noted) pa rameter sym bol test cond itions min . typ. max. unit sta tic drain-source brea kdow n voltage v ds v gs = 0 v, i d = 250 a 600 - - v v ds te mperatur e coefficient ' v ds /t j reference to 25 c, i d = 1 ma - 0 .70 - v/c gate-source threshold voltage v gs (th) v ds = v gs , i d = 250 a 2.0 - 4.0 v gate-source leakage i gss v gs = r 20 - - 100 n a ze ro gate voltage drain current i d ss v ds = 600 v , v gs = 0 v - - 100 a v ds = 480 v , v gs = 0 v, t j = 125 c - - 500 dr ain-source on-state resistance r ds (on) v gs = 10 v i d = 3.7 a b -- 2.2 : fo rward transconductance g fs v ds = 100 v , i d = 3.7 a b 3.7 - - s dynam ic input capacitance c iss v gs = 0 v v ds = 25 v f = 1.0 mhz, see fig. 5 - 1100 - pf output capacitance c oss - 140 - rev erse transfer capacitance c rss -1 5- total gate charge q g v gs = 10 v i d = 4 a, v ds = 360 v , see fig. 6 and 13 b -- 39 nc gate-so urce charge q gs -- 10 gate-drain charge q gd -- 19 turn-o n delay time t d(on ) v dd = 300 v, i d = 4 a r g = 9.1 : , r d = 47 : , see fig. 10 b -1 2- ns rise ti me t r -2 0- turn-o ff delay time t d(of f) -2 7 - fa ll t i me t f -1 7- internal drain inductance l d b etween l ead, 6 mm (0.25") from package and center of die contact -4.5- nh internal source inductance l s -7 .5- d rain-source body diode characteristics continuous source-dr ain diode current i s mosfet symbol sh owing the inte gral reverse p - n junction diode --4.0 a pulsed diode forward current a i sm -- 25 body diode voltage v sd t j = 25 c, i s = 4 a, v gs = 0 v b -- 1.5v bo dy diode reverse recovery time t rr t j = 25 c, i f = 4 a , di/dt = 100 a/s b - 440 680 ns bod y diode reverse recovery charge q rr -2 .13. 2c forward turn-on time t on intrinsic turn-on time is negligibl e (turn-on is dominated by l s and l d ) d s g s d g zzzglqwhnms '7 31'731)'781'7/1
3 typica l ch aracteristics (25 c, unless otherwise noted) fig. 1 - ty pical output characteristics, t c = 25 c fig. 2 - typical output characteristics, t c = 150 c fig. 3 - typ ical transfer characteristics fig. 4 - normalized on-resistance vs. temperature 91114_01 bottom to p v gs 15 v 10 v 8.0 v 7.0 v 6.0 v 5.5 v 5.0 v 4.5 v 20 s pulse width t c = 25 c 4.5 v v ds , drain-to-source voltage (v) i d , drain current (a) 10 0 10 1 10 1 10 0 10 -1 10 -2 10 -2 10 -1 10 2 10 1 10 0 10 -1 10 0 10 1 v ds , drain-to-source voltage (v) i d , drain current (a) bottom to p v gs 15 v 10 v 8.0 v 7.0 v 6.0 v 5.5 v 5.0 v 4.5 v 20 s pulse width t c = 150 c 91114_02 4.5 v 10 -2 10 -2 10 -1 10 2 20 s pulse width v ds = 100 v 10 1 10 0 10 -1 i d , drain current (a) v gs , gate-to-source v oltage (v) 5678910 4 25 c 150 c 91114_03 i d = 4 a v gs = 10 v 3.0 0.0 0.5 1.0 1.5 2.0 2.5 t j , junction temper ature (c) r ds(on) , drain-to-source on resistance (normalized) 91114_04 - 60 - 40 - 20 0 20 40 60 80 100 120 140 160 3.5 www.din-tek.jp dt p4n60/DTP4N60F/dtu4n60/dtl4n60
4 fig. 5 - typi c al capacitance vs. drain-to-source voltage fig. 6 - typical gate charge vs. gate-to-source voltage fig. 7 - typical source-drain diode forward voltage fig. 8 - maximum safe operating area 2400 2000 1600 1200 0 400 800 10 0 10 1 capacitance (pf) v ds , dr ain-to-source v oltage (v) c iss c rss c oss v gs = 0 v, f = 1 mhz c iss = c gs + c gd , c ds shorted c rss = c gd c oss = c ds + c gd 91114_05 q g , total gate charge (nc) v gs , gate-to-source voltage (v) 20 16 12 8 0 4 0 8 40 32 24 16 v ds = 180 v v ds = 240 v f or test circuit see figure 13 v ds = 300 v 91114_06 i d = 3.2 a 10 1 10 0 v sd , source-to-drain voltage (v) i sd , reverse drain current (a) 0.6 1.4 1.2 1.0 0.8 25 c 150 c v gs = 0 v 91114_07 10 s 100 s 1 ms 10 ms operation in this area limited by r ds(on) v ds , dr ain-to-source voltage (v) i d , dr ain current (a) t c = 25 c t j = 150 c single pulse 10 -2 10 3 0.1 2 5 0.1 2 5 1 2 5 10 2 5 25 1 25 10 25 10 2 25 10 3 25 10 4 91114_08 10 2 2 5 www.din-tek.jp dt p4n60/DTP4N60F/dtu4n60/dtl4n60
5 fig. 9 - maximum drain current vs . case temperatur e fig. 10a - switching time test circuit fig. 10b - switching time waveforms fig. 11 - maximum effective transient thermal impedance, junction-to-case i d , drain current (a) t c , case temperature (c) 0.0 2.5 3.0 3.5 4.0 5.0 25 150 125 100 75 50 91114_09 1.0 2.0 pulse width 1 s duty factor 0.1 % r d v gs r g d.u.t. 10 v + - v ds v dd v ds 90 % 10 % v gs t d(on) t r t d(off) t f 10 1 0.1 10 -2 10 -5 10 -4 10 -3 10 -2 0.1 1 10 p dm t 1 t 2 t 1 , rectangular pulse duration (s) thermal response (z thjc ) notes: 1. duty factor, d = t 1 /t 2 2. peak t j = p dm x z thjc + t c single pulse (thermal response) 0 ? 0.5 0.2 0.1 0.05 0.02 0.01 91114_11 www.din-tek.jp dt p4n60/DTP4N60F/dtu4n60/dtl4n60
6 fig. 12a - un cl amped inductive test circuit fig. 12b - unclamped inductive waveforms fig. 12c - maximum avalanche energy vs. drain current fig. 13a - basic gate charge waveform fig. 13b - gate charge test circuit r g i as 0.01 t p d.u.t. l v ds + - v dd 10 v var y t p to obtain required i as i as v ds v dd v ds t p 1200 0 200 400 600 800 1000 25 150 125 100 75 50 starting t j , junction temper ature (c) e as , single pulse energy (mj) bottom to p i d 1.8 a 2.9 a 4 a v dd = 50 v 91114_12c q gs q gd q g v g charge 10 v d.u.t. 3 ma v gs v ds i g i d 0.3 f 0.2 f 50 k 12 v current regulator current sampling resistors same type as d.u.t. + - www.din-tek.jp dt p4n60/DTP4N60F/dtu4n60/dtl4n60
1 to-220ab notes * m = 1.32 mm to 1.62 mm (dim ension including protrusion) heatsink hole for hvm m * 3 2 1 l l(1) d h(1) q ? p a f j(1) b(1) e(1) e e b c millimeters inches d im. min. max. min. max. a 4.25 4.65 0.167 0.183 b 0.69 1.01 0.027 0.040 b(1) 1.20 1.73 0.047 0.068 c 0.36 0.61 0.014 0.024 d 14.85 15.49 0.585 0.610 e 10.04 10.51 0.395 0.414 e 2.41 2.67 0.095 0.105 e(1) 4.88 5.28 0.192 0.208 f 1.14 1.40 0.045 0.055 h(1) 6.09 6.48 0.240 0.255 j(1) 2.41 2.92 0.095 0.115 l 13.35 14.02 0.526 0.552 l(1) 3.32 3.82 0.131 0.150 ? p 3.54 3.94 0.139 0.155 q 2.60 3.00 0.102 0.118 ecn: x12-0208-rev. n, 08-oct-12 dwg: 5471 package information www.din-tek.jp
1 to-220 fullp ak (high voltage) no tes 1. to be used only for process drawing. 2. these dimensions apply to all to-220, fullpak leadframe versions 3 leads. 3. all critical dimensions should c meet c pk > 1.33. 4. all d imensions include bur rs and plating thickness. 5. no chipping or package damage. e b n d1 l e b 2 b 3 ? p l1 d3 d c a2 u v a1 a mill imeters inches d im. min. max. min. max. a 4.570 4.830 0.180 0.190 a1 2.570 2.830 0.101 0.111 a2 2.510 2.850 0.099 0.112 b 0.622 0.890 0.024 0.035 b2 1.229 1.400 0.048 0.055 b3 1.229 1.400 0.048 0.055 c 0.440 0.629 0.017 0.025 d 8.650 9.800 0.341 0.386 d1 15.88 16.120 0.622 0.635 d3 12.300 12.920 0.484 0.509 e 10.360 10.630 0.408 0.419 e 2.54 bsc 0.100 bsc l 13.200 13.730 0.520 0.541 l1 3.100 3.500 0.122 0.138 n 6.050 6.150 0.238 0.242 ? p 3.050 3.450 0.120 0.136 u 2.400 2.500 0.094 0.098 v 0.400 0.500 0.016 0.020 ecn: x09-0126-rev. b, 26-oct-09 dwg: 5972 package information www.din-tek.jp
1 to-252aa case outline note ? d imension l3 is for reference only. l3 d l4 l5 b b2 e1 e1 d1 c a1 gage plane height (0.5 mm) e b3 e c2 a l h millimeters i n ches dim. min. max. min. max. a 2.18 2.38 0.086 0.094 a1 - 0.127 - 0.005 b 0.64 0.88 0.025 0.035 b2 0.76 1.14 0.030 0.045 b3 4.95 5.46 0.195 0.215 c 0.46 0.61 0.018 0.024 c2 0.46 0.89 0.018 0.035 d 5.97 6.22 0.235 0.245 d1 5.21 - 0.205 - e 6.35 6.73 0.250 0.265 e1 4.32 - 0.170 - h 9.40 10.41 0.370 0.410 e 2.28 bsc 0.090 bsc e1 4.56 bsc 0.180 bsc l 1.40 1.78 0.055 0.070 l3 0.89 1.27 0.035 0.050 l4 - 1.02 - 0.040 l5 1.14 1.52 0.045 0.060 ecn: x12-0247 -rev. m, 24-dec-12 dwg: 5347 package information www.din-tek.jp
note: dimension l3 is for reference only. l2 b1 b b2 e l3 l1 l d c a1 c1 a e 1
dim min max min max a 2.21 2.38 0.087 0.094 a1 0.89 1.14 0.035 0.045 b 0.71 0.89 0.028 0.035 b1 0.76 1.14 0.030 0.045 b2 5.23 5.43 0.206 0.214 c 0.46 0.58 0.018 0.023 c1 0.46 0.58 0.018 0.023 d 5.97 6.22 0.235 0.245 e 6.48 6.73 0.255 0.265 e 2.28 bs c 0.090 bsc l 8.89 9.53 0.350 0.375 l1 1.91 2.28 0.075 0.090 l2 0.89 1.27 0.035 0.050 l3 1.15 1.52 0.045 0.060 ecn: s-03946?rev. e, 09-jul-01 dwg: 5346 www. gd\vhplms package information www.din-tek.jp
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